> git_commit.sh ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 00:05:11 up 8:51, 2 users, load average: 0.57, 0.50, 0.41

This commit is contained in:
tracer-ysyx 2024-01-05 00:05:11 +08:00 committed by xinyangli
parent 7e177f8b04
commit 3b7e367af1
5 changed files with 81 additions and 24 deletions

29
npc/CMakeLists.txt Normal file
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@ -0,0 +1,29 @@
cmake_minimum_required(VERSION 3.10)
project(NPC_xin)
find_package(verilator)
if (NOT verilator_FOUND)
message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable")
endif()
if(NOT DEFINED NVBOARD_HOME)
set(NVBOARD_HOME get_filename_component(real_path "../nvboard" REALPATH))
endif()
add_library(nvboard STATIC IMPORTED)
set_target_properties(bar PROPERTIES
IMPORTED_LOCATION "${NVBOARD_HOME}/build/nvboard.a"
INTERFACE_INCLUDE_DIRECTORIES "${CMAKE_SOURCE_DIR}/include/libbar"
)
add_executable(Main csrc/main.cpp)
add_executable(Main_nvboard csrc_nvboard/main.cpp)
verilate(Main
COVERAGE TRACE
SOURCES build/chisel/Main.sv build/chisel/RegisterFile.sv)
verilate(Main_nvboard
COVERAGE TRACE
SOURCES build/chisel/Main.sv build/chisel/RegisterFile.sv)

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@ -1,6 +1,5 @@
NVBOARD_HOME ?= $(abspath ../nvboard)
PREFIX ?= build
OBJDIR = $(PREFIX)/obj
CHISEL_VDIR := $(PREFIX)/chisel
CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
@ -12,7 +11,10 @@ CHISEL_TOP_PACKAGE := learning
CHISEL_TOP_MODULE := Main
CHISEL_TARGET := verilog
SUBMAKE = $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
SUBDIRS := obj nvobj
SUBDIRS := $(addprefix $(PREFIX),$(SUBDIRS))
SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# Pretty printing
MAKEFLAGS += --no-print-directory
@ -24,21 +26,19 @@ endef
all: sim-bin nvboard-bin
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc)
$(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
$(SUBDIRS):%: %/V$(CHISEL_TOP_MODULE).mk
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
@$(call colorize,"SUBMAKE",$^)
$(MAKE) -s -C $(OBJDIR) -f $(notdir $(SUBMAKE)) V$(CHISEL_TOP_MODULE)
$(MAKE) -s -C $(dir $@) -f $< $(notdir $@)
$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src
@$(call colorize,"VERILATOR",$^)
@$(call colorize,"VERILATOR",$@)
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(OBJDIR):
mkdir -p $(OBJDIR)
mkdir -p $@
$(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
@$(call colorize,"CIRCT",$^)
@ -52,14 +52,18 @@ compile_commands.json: clean
.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard
OBJDIR = $(PREFIX)/nvobj
SUBMAKE = $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
#his awkward way to find nvboard.a
CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
@echo $(OBJDIR)
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc)
$(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
nvboard-bin: OBJDIR := $(PREFIX)/nvobj
nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# TODO: fix this awkward way to find nvboard.a
nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
@echo $(SUBMAKE) $(OBJDIR)
sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)

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@ -2,7 +2,6 @@
#include <cassert>
#include <cstdlib>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <VMain.h>
#include <nvboard.h>

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@ -34,10 +34,31 @@
"type": "github"
}
},
"nur-xin": {
"inputs": {
"nixpkgs": [
"nixpkgs"
]
},
"locked": {
"lastModified": 1704380403,
"narHash": "sha256-eElBXx8ocUCVg6LuHBUXSfCRKYRZfbwURIXcgL/ciJY=",
"ref": "refs/heads/master",
"rev": "2e7a57373f52999d579dcebb1202dc731d71ef35",
"revCount": 139,
"type": "git",
"url": "https://git.xinyang.life/xin/nur.git"
},
"original": {
"type": "git",
"url": "https://git.xinyang.life/xin/nur.git"
}
},
"root": {
"inputs": {
"flake-utils": "flake-utils",
"nixpkgs": "nixpkgs"
"nixpkgs": "nixpkgs",
"nur-xin": "nur-xin"
}
},
"systems": {

View file

@ -2,17 +2,23 @@
inputs = {
nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
flake-utils.url = "github:numtide/flake-utils";
nur-xin = {
url = "git+https://git.xinyang.life/xin/nur.git";
inputs.nixpkgs.follows = "nixpkgs";
};
};
outputs = { self, ... }@inputs: with inputs;
flake-utils.lib.eachDefaultSystem (system:
let pkgs = nixpkgs.legacyPackages.${system}; in
let
pkgs = nixpkgs.legacyPackages.${system} //
{ nur.xin = nur-xin.legacyPackages.${system}; };
in
{
devShells.default = pkgs.mkShell {
packages = with pkgs; [
gtkwave
gdb
jq
bear
clang-tools
rnix-lsp
@ -20,16 +26,14 @@
];
nativeBuildInputs = with pkgs; [
cmake
verilator
gcc
python3
scala
nur.xin.nvboard
self.packages.${system}.circt
];
buildInputs = with pkgs; [
SDL2
SDL2_image
jre
];