diff --git a/npc/Makefile b/npc/Makefile
index c1b395e..c97a404 100644
--- a/npc/Makefile
+++ b/npc/Makefile
@@ -10,12 +10,12 @@ sim: all
 	$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
 	@echo "Running" $(OBJDIR)/Vexample "..."
 	@echo "================================"
-	$(OBJDIR)/Vexample
+	@$(OBJDIR)/Vexample
 	
 
 $(OBJDIR): $(VSRC) $(CPPSRC)
 	mkdir -p $(OBJDIR)
-	verilator --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
+	verilator --trace --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
 
 include ../Makefile
 
diff --git a/npc/trace/main.cpp b/npc/trace/main.cpp
new file mode 100644
index 0000000..a62b9be
--- /dev/null
+++ b/npc/trace/main.cpp
@@ -0,0 +1,32 @@
+#include "verilated_vcd_c.h"
+#include "Vexample.h"
+#include "verilated.h"
+
+int main(int argc, char **argv, char **env) {
+}
+
+int main(int argc, char **argv, char **env) {
+    Verilated::commandArgs(argc, argv);
+    Verilated::traceEverOn(true);
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    Vexample *top = new Vexample;
+    int round = 100;
+    while (round--) {
+        int a = rand() & 1;
+        int b = rand() & 1;
+        top->a = a;
+        top->b = b;
+        top->eval();
+        printf("a = %d, b = %d, f = %d\n", a, b, top->f);
+        assert(top->f == (a ^ b));
+    }
+    exit(0);
+    topp->trace (tfp, 99);
+    tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
+    ...
+    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+        main_time += #;
+        tfp->dump (main_time);
+    }
+    tfp->close();
+}
\ No newline at end of file