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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:17:34  up  23:15,  2 users,  load average: 0.33, 0.36, 0.48
This commit is contained in:
tracer-ysyx 2023-12-23 20:17:34 +08:00 committed by xinyangli
parent ee94bc8eea
commit 386c3ce04c
1 changed files with 4 additions and 9 deletions
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13
npc/Makefile
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@ -7,23 +7,18 @@ VERILATOR_FLAGS := --cc --exe
all: sim
sim: $(OBJDIR) $(VSRC) $(CPPSRC) $(SUBMAKE)
sim: VERILATOR_FLAGS += --trace
sim: $(VSRC) $(CPPSRC) $(SUBMAKE)
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample
trace: VERILATOR_FLAGS += --trace
trace: $(OBJDIR) $(VSRC) $(CPPSRC) $(SUBMAKE)
$(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!!
@$(OBJDIR)/Vexample
$(SUBMAKE): $(VSRC) $(CPPSRC)
$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR)
verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
$(OBJDIR): $(VSRC) $(CPPSRC)
$(OBJDIR):
mkdir -p $(OBJDIR)
verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile