From 2f6b381c9deb374fa91614e7c9ec315ad00f9dab Mon Sep 17 00:00:00 2001
From: tracer-ysyx <tracer@ysyx.org>
Date: Wed, 13 Mar 2024 13:38:28 +0800
Subject: [PATCH] =?UTF-8?q?>=20build=5Fflow=5FVFlow=20=20ysyx=5F22040000?=
 =?UTF-8?q?=20=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20?=
 =?UTF-8?q?#1-NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:1?=
 =?UTF-8?q?1=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2013:38:28=20=20up?=
 =?UTF-8?q?=20=20=203:14,=20=202=20users,=20=20load=20average:=204.33,=202?=
 =?UTF-8?q?.50,=201.64?=
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---
 npc/core/src/main/scala/Main.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 969166c..4455a0a 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -124,5 +124,8 @@ class Flow extends Module {
   alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
   alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
   alu.in.b := reg.out.src(1)
+
+  val pcValue = IO(Output(chiselTypeOf(pc.out)))
+  pcValue := pc.out
   dontTouch(control.out)
 }