diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 969166c..4455a0a 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -124,5 +124,8 @@ class Flow extends Module {
   alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
   alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
   alu.in.b := reg.out.src(1)
+
+  val pcValue = IO(Output(chiselTypeOf(pc.out)))
+  pcValue := pc.out
   dontTouch(control.out)
 }