diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 41b4ba4..9f601e7 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -3,9 +3,12 @@ package npc
 import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
 import chisel3.util.{SRAM}
+import chisel3.util.experimental.decode.{decoder, TruthTable, QMCMinimizer}
 import chisel3.stage.ChiselOption
-import npc.util.{ KeyboardSegController, RegisterFile }
-import flowpc.components.{ProgramCounter, ProgramCounterSel}
+import npc.util.{ KeyboardSegController }
+import flowpc.components.RegisterFile
+import chisel3.util.log2Ceil
+import chisel3.util.BitPat
 
 class Switch extends Module {
   val io = IO(new Bundle {
@@ -33,12 +36,32 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
-object Opcode extends ChiselEnum {
+object RV32Inst extends ChiselEnum {
   val addi = Value("b0010011".U)
+  val inv = Value("b0000000".U)
 }
 
-class Control extends Bundle {
-  
+object InstType extends ChiselEnum {
+  val R, I, S, B, U, J = Value
+}
+
+class RegControl(width: Int) extends Bundle {
+  object RegWriteDataSel extends ChiselEnum {
+    val ALUOut = Value
+  }
+  val T = RegWriteDataSel
+  val writeEnable = Output(Bool()) 
+  val writeSelect = Output(this.T())
+}
+
+class Control(width: Int) extends Bundle {
+  val inst = IO(Input(UInt(width.W)))
+  val out = decoder(QMCMinimizer, inst, TruthTable(
+    Map(
+      BitPat(Opcode.addi.asUInt) -> BitPat("b00001")
+    ), BitPat("b?????")))
+  val regControl = new RegControl(width)
+
 }
 
 class Flowpc extends Module {
diff --git a/npc/core/src/main/scala/RegisterFile.scala b/npc/core/src/main/scala/RegisterFile.scala
index fbf8a94..8bb3cc0 100644
--- a/npc/core/src/main/scala/RegisterFile.scala
+++ b/npc/core/src/main/scala/RegisterFile.scala
@@ -1,25 +1,28 @@
-package npc.util
+package flowpc.components
 
 import chisel3._
+import chisel3.util.log2Ceil
+import chisel3.util.UIntToOH
 
-class RegisterFile(readPorts: Int) extends Module {
-  require(readPorts >= 0)
-  val io = IO(new Bundle {
-    val writeEnable = Input(Bool())
-    val writeAddr = Input(UInt(5.W))
-    val writeData = Input(UInt(32.W))
-    val readAddr = Input(Vec(readPorts, UInt(5.W)))
-    val readData = Output(Vec(readPorts, UInt(32.W)))
+class RegisterFile(width: Int, numRegisters: Int, numReadPorts: Int) extends Module {
+  require(numReadPorts >= 0)
+  val writePort = IO(new Bundle {
+    val enable = Input(Bool())
+    val addr = Input(UInt(log2Ceil(width).W))
+    val data = Input(UInt(width.W))
   })
+  val readPorts = IO(Vec(numReadPorts, new Bundle {
+    val addr = Input(UInt(log2Ceil(width).W))
+    val data = Output(UInt(width.W))
+  }))
 
-  val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
-  for (i <- 1 until 32) {
-    regFile(i) := regFile(i)
+  val regFile = RegInit(VecInit(Seq.fill(numRegisters)(0.U(32.W))))
+  val writeAddrOH = UIntToOH(writePort.addr)
+  for ((reg, i) <- regFile.zipWithIndex) {
+    reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
   }
-  regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
-  regFile(0) := 0.U
 
-  for (i <- 0 until readPorts) {
-    io.readData(i) := regFile(io.readAddr(i))
+  for (readPort <- readPorts) {
+    readPort.data := regFile(readPort.addr)
   }
 }