From 187aa3fc236dfefa5788e2dffa6e856edb020f49 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Wed, 10 Jan 2024 20:48:55 +0800 Subject: [PATCH] =?UTF-8?q?>=20build=5Fnpc=5FVKeyboard=5Fnvboard=20=20ysyx?= =?UTF-8?q?=5F22040000=20=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite?= =?UTF-8?q?=206.1.69=20#1-NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Wed=20Dec=2020?= =?UTF-8?q?=2016:00:29=20UTC=202023=20x86=5F64=20GNU/Linux=20=20=2020:48:5?= =?UTF-8?q?5=20=20up=202=20days=2019:49,=20=202=20users,=20=20load=20avera?= =?UTF-8?q?ge:=200.84,=200.81,=200.86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/SegGenerator.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/npc/core/src/main/scala/SegGenerator.scala b/npc/core/src/main/scala/SegGenerator.scala index 574cd95..ecdb4a6 100644 --- a/npc/core/src/main/scala/SegGenerator.scala +++ b/npc/core/src/main/scala/SegGenerator.scala @@ -34,7 +34,7 @@ class SegGenerator(seg_count: Int) extends Module { val keycode = RegInit(0.U(8.W)) val counter = Counter(0xFF) - val release_state = false.B + val release_state = RegInit(Bool(), false.B) when(io.keycode.ready && io.keycode.valid) { when(io.keycode.bits === 0xF0.U) { release_state := true.B