From 16ff4fa42e94b3ef93728f126084cbbb4a074517 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Tue, 26 Mar 2024 10:40:24 +0800 Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20#1-?= =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11?= =?UTF-8?q?=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2010:40:24=20=20up?= =?UTF-8?q?=20=2020:16,=20=202=20users,=20=20load=20average:=200.08,=200.1?= =?UTF-8?q?7,=200.25?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/Main.scala | 3 --- 1 file changed, 3 deletions(-) diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 95b9e61..bf1ffab 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -33,12 +33,9 @@ class Keyboard extends Module { io.segs := seg_handler.io.segs } -<<<<<<< Updated upstream -======= class Flowpc extends Module { val io = IO(new Bundle { }) val register_file = new RegisterFile(readPorts = 2); val pc = new ProgramCounter(32); val adder = new SRAM() } ->>>>>>> Stashed changes