From 0b34b19bdfdbc43725649d0a925f48bb5b95c8bb Mon Sep 17 00:00:00 2001 From: xinyangli Date: Mon, 8 Jan 2024 18:29:28 +0800 Subject: [PATCH] implement keyboard controller --- npc/Makefile | 102 -------------------- npc/core/.gitignore | 13 +++ npc/{ => core}/.scalafmt.conf | 0 npc/core/src/main/scala/Main.scala | 121 ++++++++++++++++++++++++ npc/core/src/main/scala/Reg.scala | 64 ------------- npc/core/src/test/scala/Main.scala | 147 +++++++++++++++++++++++++++++ npc/core/src/test/scala/Reg.scala | 71 -------------- npc/flake.nix | 3 + 8 files changed, 284 insertions(+), 237 deletions(-) delete mode 100644 npc/Makefile create mode 100644 npc/core/.gitignore rename npc/{ => core}/.scalafmt.conf (100%) create mode 100644 npc/core/src/main/scala/Main.scala delete mode 100644 npc/core/src/main/scala/Reg.scala create mode 100644 npc/core/src/test/scala/Main.scala delete mode 100644 npc/core/src/test/scala/Reg.scala diff --git a/npc/Makefile b/npc/Makefile deleted file mode 100644 index 34e6e03..0000000 --- a/npc/Makefile +++ /dev/null @@ -1,102 +0,0 @@ -NVBOARD_HOME ?= $(abspath ../nvboard) -PREFIX ?= build -CHISEL_VDIR := $(PREFIX)/chisel - -CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) - -VERILATOR_FLAGS := --cc --exe -LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image - -CHISEL_TOP_PACKAGE := learning -CHISEL_TOP_MODULE := Main -CHISEL_TARGET := verilog - -SUBDIRS := obj nvobj -SUBDIRS := $(addprefix $(PREFIX),$(SUBDIRS)) - -SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk - -# Pretty printing -MAKEFLAGS += --no-print-directory -GREEN := \e[32m -NC := \e[0m -define colorize - printf '$(GREEN)'$(1)'$(NC) $(2)\n' -endef - -all: sim-bin nvboard-bin - -$(SUBDIRS):%: %/V$(CHISEL_TOP_MODULE).mk - verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS) - -$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE) - @$(call colorize,"SUBMAKE",$^) - $(MAKE) -s -C $(dir $@) -f $< $(notdir $@) - -$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src - @$(call colorize,"VERILATOR",$@) - verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS) - -$(OBJDIR): - mkdir -p $@ - -$(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala) - @$(call colorize,"CIRCT",$^) - sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)" - -compile_commands.json: clean - $(MAKE) $(CHISEL_VDIR)/filelist.f - $(RM) compile_commands.json - bear --append -- $(MAKE) nvboard-bin - bear --append -- $(MAKE) sim-bin - -.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard - -SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp) -NXDC_FILES := $(abspath constr/top.nxdc) -$(SRC_AUTO_BIND): $(NXDC_FILES) - NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@ - -nvboard-bin: OBJDIR := $(PREFIX)/nvobj -nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk -# TODO: fix this awkward way to find nvboard.a -nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a -nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE) - @echo $(SUBMAKE) $(OBJDIR) - -sim-bin: VERILATOR_FLAGS += --trace -sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE) - -chisel-src: $(CHISEL_VDIR)/filelist.f - $(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv)) - @echo "GENERATED: $(CHISEL_VSRC)" - -ifneq (,$(wildcard ../Makefile)) -include ../Makefile -else -define git_commit # not in ICS subfolder, no tracing -endef -endif - -git_trace_sim: - $(call git_commit, "sim RTL") - -git_trace_nvboard: - $(call git_commit, "nvboard") - -nvboard: OBJDIR := $(PREFIX)/nvobj -nvboard: nvboard-bin git_trace_nvboard - @echo "Running NVBoard ..." - @echo "================================" - @NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE) - -sim: sim-bin git_trace_sim - @echo "Running verilator sim ..." - @echo "================================" - @$(OBJDIR)/V$(CHISEL_TOP_MODULE) - -clean: - $(RM) -r $(PREFIX) - -$(V).SILENT: diff --git a/npc/core/.gitignore b/npc/core/.gitignore new file mode 100644 index 0000000..014f5dc --- /dev/null +++ b/npc/core/.gitignore @@ -0,0 +1,13 @@ +# Created by https://www.toptal.com/developers/gitignore/api/scala +# Edit at https://www.toptal.com/developers/gitignore?templates=scala + +### Scala ### +*.class +*.log + +# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml +hs_err_pid* + +# End of https://www.toptal.com/developers/gitignore/api/scala + +test_run_dir/ diff --git a/npc/.scalafmt.conf b/npc/core/.scalafmt.conf similarity index 100% rename from npc/.scalafmt.conf rename to npc/core/.scalafmt.conf diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala new file mode 100644 index 0000000..4e427f2 --- /dev/null +++ b/npc/core/src/main/scala/Main.scala @@ -0,0 +1,121 @@ +package npc + +import chisel3._ +import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} +import chisel3.stage.ChiselOption + +class RegisterFile(readPorts: Int) extends Module { + require(readPorts >= 0) + val io = IO(new Bundle { + val writeEnable = Input(Bool()) + val writeAddr = Input(UInt(5.W)) + val writeData = Input(UInt(32.W)) + val readAddr = Input(Vec(readPorts, UInt(5.W))) + val readData = Output(Vec(readPorts, UInt(32.W))) + }) + + val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W)))) + for (i <- 1 until 32) { + regFile(i) := regFile(i) + } + regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr)) + regFile(0) := 0.U + + for (i <- 0 until readPorts) { + io.readData(i) := regFile(io.readAddr(i)) + } +} + +class ALUGenerator(width: Int) extends Module { + require(width >= 0) + val io = IO(new Bundle { + val a = Input(UInt(width.W)) + val b = Input(UInt(width.W)) + val op = Input(UInt(4.W)) + val out = Output(UInt(width.W)) + }) + + val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub + val add = io.a + adder_b + val and = io.a & io.b + val not = ~io.a + val or = io.a | io.b + val xor = io.a ^ io.b + val slt = io.a < io.b + val eq = io.a === io.b + + io.out := MuxLookup(io.op, 0.U)(Seq( + 0.U -> add, + 1.U -> add, // add with b reversed + 2.U -> not, + 3.U -> and, + 4.U -> or, + 5.U -> xor, + 6.U -> slt, + 7.U -> eq, + )) +} + +class Test extends Module { + val io = IO(new Bundle { + val in = Input(UInt(32.W)) + val out = Output(UInt(32.W)) + }) + + val regFile = Module(new RegisterFile(2)) + regFile.io.writeEnable := true.B + regFile.io.writeAddr := 1.U + regFile.io.writeData := io.in + regFile.io.readAddr(0) := 0.U + regFile.io.readAddr(1) := 1.U + io.out := regFile.io.readData(1) +} + +class KeyboardController extends Module { + val io = IO(new Bundle { + val ps2_clk = Input(Bool()) + val ps2_data = Input(UInt(1.W)) + val out = Decoupled(UInt(8.W)) + }) + val queue_io = Wire(Flipped(Decoupled(UInt(8.W)))) + queue_io.valid := true.B + queue_io.bits := 0.B + val queue = Queue(queue_io, entries = 8) + io.out <> queue + + // valid only on the clock negedge of ps2_clk + val ps2_clk_valid = RegNext(io.ps2_clk, false.B) & ~io.ps2_clk + val cycle_counter = Counter(11) + val concated_data = RegInit(0.U(8.W)) + val is_receiving = RegInit(Bool(), false.B) + + when(io.ps2_clk && io.ps2_data === 1.U) { + // Start receiving data + is_receiving := true.B + } + + when(is_receiving && ps2_clk_valid) { + cycle_counter.inc() + when(cycle_counter.value < 9.U && cycle_counter.value > 0.U) { + concated_data := (concated_data << 1) | io.ps2_data + } + when(cycle_counter.value === 10.U) { + is_receiving := false.B + } + } + + when(is_receiving) { + queue_io.noenq() + }.otherwise{ + queue_io.enq(Reverse(concated_data)) + } +} + +class Switch extends Module { + val io = IO(new Bundle { + val sw = Input(Vec(2, Bool())) + val out = Output(Bool()) + }) + + io.out := io.sw(0) ^ io.sw(1) +} diff --git a/npc/core/src/main/scala/Reg.scala b/npc/core/src/main/scala/Reg.scala deleted file mode 100644 index dd5dc4f..0000000 --- a/npc/core/src/main/scala/Reg.scala +++ /dev/null @@ -1,64 +0,0 @@ -package npc - -import chisel3._ -import chisel3.stage.ChiselOption - -class RegisterFile(readPorts: Int) extends Module { - require(readPorts >= 0) - val io = IO(new Bundle { - val writeEnable = Input(Bool()) - val writeAddr = Input(UInt(5.W)) - val writeData = Input(UInt(32.W)) - val readAddr = Input(Vec(readPorts, UInt(5.W))) - val readData = Output(Vec(readPorts, UInt(32.W))) - }) - - val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W)))) - for (i <- 1 until 32) { - regFile(i) := regFile(i) - } - regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr)) - regFile(0) := 0.U - - for (i <- 0 until readPorts) { - io.readData(i) := regFile(io.readAddr(i)) - } -} - -class MuxGenerator(width: Int, nInput: Int) extends Module { - require(width >= 0) - require(nInput >= 1) - require(nInput.toBinaryString.map(_ - '0').sum == 1) - - val io = IO(new Bundle { - val in = Input(Vec(nInput, UInt(width.W))) - val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W)) - val out = Output(UInt(width.W)) - }) - - io.out := io.in(io.sel) -} - -class Test extends Module { - val io = IO(new Bundle { - val in = Input(UInt(32.W)) - val out = Output(UInt(32.W)) - }) - - val regFile = Module(new RegisterFile(2)) - regFile.io.writeEnable := true.B - regFile.io.writeAddr := 1.U - regFile.io.writeData := io.in - regFile.io.readAddr(0) := 0.U - regFile.io.readAddr(1) := 1.U - io.out := regFile.io.readData(1) -} - -class Switch extends Module { - val io = IO(new Bundle { - val sw = Input(Vec(2, Bool())) - val out = Output(Bool()) - }) - - io.out := io.sw(0) ^ io.sw(1) -} diff --git a/npc/core/src/test/scala/Main.scala b/npc/core/src/test/scala/Main.scala new file mode 100644 index 0000000..9b0cec4 --- /dev/null +++ b/npc/core/src/test/scala/Main.scala @@ -0,0 +1,147 @@ +package npc + +import chisel3._ +import chiseltest._ +import org.scalatest.freespec.AnyFreeSpec +import chiseltest.simulator.ChiselBridge +import chiseltest.simulator.WriteVcdAnnotation + +class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester { + "RegisterFile should work" - { + "with 2 read ports" in { + test(new RegisterFile(2)) { c => + def readExpect(addr: Int, value: Int, port: Int = 0): Unit = { + c.io.readAddr(port).poke(addr.U) + c.io.readData(port).expect(value.U) + } + def write(addr: Int, value: Int): Unit = { + c.io.writeEnable.poke(true.B) + c.io.writeData.poke(value.U) + c.io.writeAddr.poke(addr.U) + c.clock.step(1) + c.io.writeEnable.poke(false.B) + } + // everything should be 0 on init + for (i <- 0 until 32) { + readExpect(i, 0, port = 0) + readExpect(i, 0, port = 1) + } + + // write 5 * addr + 3 + for (i <- 0 until 32) { + write(i, 5 * i + 3) + } + + // check that the writes worked + for (i <- 0 until 32) { + readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2) + } + } + } + } +} + +class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester { + "With 32 width, " - { + val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1 + val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16) + val mask = BigInt("FFFFFFFF", 16) + val oprands: List[(BigInt, BigInt)] = List( + (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2) + ) + val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map( + 0 -> ((a: BigInt, b: BigInt) => (a + b) & mask), + 1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask), + 2 -> ((a, _) => not(a)), + 3 -> (_ & _), + 4 -> (_ | _), + 5 -> (_ ^ _), + 6 -> ((a, b) => if (a < b) 1 else 0), + 7 -> ((a, b) => if (a == b) 1 else 0), + ) + val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => { + c.io.op.poke(op.U) + oprands.foreach({ case (a, b) => + c.io.a.poke(a.U) + c.io.b.poke(b.U) + c.io.out.expect(operations(op)(a, b)) + }) + } + "add should work" in { + test(new ALUGenerator(32)) { c => validate(c, 0, oprands) } + } + "sub should work" - { + "with positive result" in { + test(new ALUGenerator(32)) { c => + validate(c, 1, oprands.filter({case (a, b) => a >= b})) + } + } + "with negative result" in { + test(new ALUGenerator(32)) { c => + validate(c, 1, oprands.filter({case (a, b) => a < b})) + } + } + } + "not should work" in { + test(new ALUGenerator(32)) { c => validate(c, 2, oprands) } + } + "and should work" in { + test(new ALUGenerator(32)) { c => validate(c, 3, oprands) } + } + "or should work" in { + test(new ALUGenerator(32)) { c => validate(c, 4, oprands) } + } + "xor should work" in { + test(new ALUGenerator(32)) { c => validate(c, 5, oprands) } + } + "compare should work" in { + test(new ALUGenerator(32)) { c => validate(c, 6, oprands) } + } + "equal should work" in { + test(new ALUGenerator(32)) { c => validate(c, 7, oprands) } + } + } +} + +class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester { + def transfer(keycode: Int, c: KeyboardController) : Unit = { + require(keycode >= 0 && keycode < 0xFF) + var cycle = 0 + var ps2_clk = true + var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 1 + var keycode_collect = 0 + + c.io.ps2_clk.poke(ps2_clk) + c.io.ps2_data.poke(1) + for (cycle <- 0 until 9) { + c.io.ps2_clk.poke(true) + c.clock.step(32) + val last_digit = keycode_remain & 1 + c.io.ps2_data.poke(last_digit) + keycode_collect = keycode_collect | (last_digit << cycle) + keycode_remain = keycode_remain >> 1 + c.io.ps2_clk.poke(false) + c.clock.step(32) + } + for (_ <- 9 until 11) { + c.io.ps2_clk.poke(true) + c.clock.step(32) + c.io.ps2_clk.poke(ps2_clk) + ps2_clk = !ps2_clk + c.io.ps2_clk.poke(false) + c.clock.step(32) + } + assert(keycode_collect >> 1 == keycode) + c.io.out.ready.poke(1) + c.clock.step(32) + c.io.out.bits.expect(keycode) + } + "Simple test" in { + test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c => + transfer(0xE4, c) + transfer(0xE4, c) + transfer(0xE4, c) + transfer(0xE4, c) + } + } +} diff --git a/npc/core/src/test/scala/Reg.scala b/npc/core/src/test/scala/Reg.scala deleted file mode 100644 index e287f48..0000000 --- a/npc/core/src/test/scala/Reg.scala +++ /dev/null @@ -1,71 +0,0 @@ -import chisel3._ -import chiseltest._ -import org.scalatest.freespec.AnyFreeSpec - -class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester { - "RegisterFile should work" - { - "with 2 read ports" in { - test(new RegisterFile(2)) { c => - def readExpect(addr: Int, value: Int, port: Int = 0): Unit = { - c.io.readAddr(port).poke(addr.U) - c.io.readData(port).expect(value.U) - } - def write(addr: Int, value: Int): Unit = { - c.io.writeEnable.poke(true.B) - c.io.writeData.poke(value.U) - c.io.writeAddr.poke(addr.U) - c.clock.step(1) - c.io.writeEnable.poke(false.B) - } - // everything should be 0 on init - for (i <- 0 until 32) { - readExpect(i, 0, port = 0) - readExpect(i, 0, port = 1) - } - - // write 5 * addr + 3 - for (i <- 0 until 32) { - write(i, 5 * i + 3) - } - - // check that the writes worked - for (i <- 0 until 32) { - readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2) - } - } - } - } -} - -class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester { - "MuxGenerator should work" - { - "when there are 2 inputs" in { - test(new MuxGenerator(8, 2)) { c => - c.io.in(0).poke(0.U) - c.io.in(1).poke(1.U) - c.io.sel.poke(0.U) - c.io.out.expect(0.U) - c.io.sel.poke(1.U) - c.io.out.expect(1.U) - } - } - "when there are 1024 inputs" in { - test(new MuxGenerator(32, 1024)) { c => - for (i <- 0 until 1024) { - c.io.in(i).poke(i.U) - } - for (i <- 0 until 1024) { - c.io.sel.poke(i.U) - c.io.out.expect(i.U) - } - } - } - } - "MuxGenerator should raise exception" - { - "when nInput is not 2^n" in { - assertThrows[IllegalArgumentException] { - test(new MuxGenerator(8, 3)) { c => } - } - } - } -} diff --git a/npc/flake.nix b/npc/flake.nix index 24e3790..b2fd2fa 100644 --- a/npc/flake.nix +++ b/npc/flake.nix @@ -19,8 +19,11 @@ packages = [ clang-tools rnix-lsp + gdb jre + + gtkwave ]; inputsFrom = [ self.packages.${system}.default ];