> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar 1 12:35:11 UTC 2024 x86_64 GNU/Linux 14:27:30 up 3 days 5:18, 2 users, load average: 1.26, 1.28, 1.31
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tracer-ysyx
parent
b1db549157
commit
0560c97eda
5 changed files with 63 additions and 49 deletions
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@ -9,10 +9,15 @@ class ALUControlInterface extends Bundle {
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val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
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}
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val op = Input(OpSelect())
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type ctrlTypes = OpSelect.Type :: HNil
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def ctrlBindPorts: ctrlTypes = {
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op :: HNil
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}
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}
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class ALU[T <: UInt](tpe: T) extends Module {
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val control = new ALUControlInterface
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val control = IO(new ALUControlInterface)
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val in = IO(new Bundle {
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val a = Input(tpe)
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val b = Input(tpe)
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@ -33,7 +38,7 @@ class ALU[T <: UInt](tpe: T) extends Module {
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import control.OpSelect._
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out.result := MuxLookup(control.op, aOpNop.asUInt)(Seq(
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out.result := MuxLookup(control.op, 0.U)(Seq(
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aOpAdd -> add,
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aOpSub -> sub,
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aOpNot -> not,
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@ -43,15 +48,10 @@ class ALU[T <: UInt](tpe: T) extends Module {
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aOpSlt -> slt,
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aOpEq -> eq
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))
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type ctrlTypes = control.OpSelect.Type :: HNil
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def ctrlBindPorts: ctrlTypes = {
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control.op :: HNil
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}
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}
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object ALU {
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def apply[T <: UInt](tpe: T): ALU[T] = {
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new ALU(tpe)
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Module(new ALU(tpe))
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}
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}
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@ -16,7 +16,7 @@ import shapeless.ops.coproduct.Prepend
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object RV32Inst {
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private val bp = BitPat
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val addi = this.bp("b??b?????_?????_?????_000_?????_00100_11")
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val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
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val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
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}
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@ -28,46 +28,57 @@ class PcControl(width: Int) extends Bundle {
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}
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import flow.components.{ RegisterFile, ProgramCounter, ALU }
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import flow.components.{ RegisterFile, RegFileInterface, ProgramCounter, ALU }
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import flow.components.{ RegControl, PcControlInterface, ALUControlInterface }
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class Control(width: Int) extends Module {
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val inst = Input(UInt(width.W))
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val reg = Flipped(RegisterFile(32, UInt(width.W), 2, 2))
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val pc = ProgramCounter(UInt(width.W))
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val alu = ALU(UInt(width.W))
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val inst = IO(Input(UInt(width.W)))
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// TODO: Add .ctrlTypes together instead of write them by hand.
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type T = Bool :: reg.control.WriteSelect.Type :: pc.SrcSelect.Type :: alu.control.OpSelect.Type :: HNil
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val reg = IO(Flipped(new RegControl))
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val pc = IO(Flipped(new PcControlInterface))
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val alu = IO(Flipped(new ALUControlInterface))
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// TODO: Add .ctrlTypes together instead of writing them by hand.
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type T = Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: HNil
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val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts
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val dstList: List[Data] = dst.toList
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val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
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val slices = reversePrefixSum.zip(reversePrefixSum.tail)
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import reg.control.WriteSelect._
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import reg.WriteSelect._
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import pc.SrcSelect._
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import alu.control.OpSelect._
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import alu.OpSelect._
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import RV32Inst._
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val ControlMapping: Array[(BitPat, T)] = Array(
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// Regs :: PC :: Exe
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// writeEnable :: writeSelect :: srcSelect ::
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(addi, false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil)
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)
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def toBits(t: T): BitPat = {
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val list: List[Data] = t.toList
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list.map(x => x.asUInt).map(x => BitPat(x)).reduce(_ ## _)
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list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduce(_ ## _)
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}
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val out = decoder(QMCMinimizer, inst, TruthTable(
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ControlMapping.map(it => (it._1, toBits(it._2))), inv))
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val default = toBits(false.B :: rAluOut :: pStaticNpc :: aOpSlt:: HNil)
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val out = decoder(QMCMinimizer, inst, TruthTable(
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ControlMapping.map(it => (it._1, toBits(it._2))), default))
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val dstList = dst.toList
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val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
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val slices = reversePrefixSum.zip(reversePrefixSum.tail)
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val srcList = slices.map(s => out(s._1 - 1, s._2))
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srcList.zip(dstList).foreach({ case (src, dst) => dst := src })
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// def m[T <: Data](src: UInt, dst: T) = dst match {
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// case dst: EnumType => dst := src.asTypeOf(chiselTypeOf(dst))
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// case dst: Data => dst := src
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// }
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srcList.zip(dstList).foreach({
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case (src, dst) => dst := src.asTypeOf(dst)
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})
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}
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class Flow extends Module {
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val io = IO(new Bundle { })
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val ram = SRAM(size=128*1024*1024, tpe=UInt(32.W), numReadPorts=2, numWritePorts=1,numReadwritePorts=0)
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val control = new Control(32)
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val control = Module(new Control(32))
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// Instruction Fetch
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ram.readPorts(0).enable := true.B
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@ -4,30 +4,33 @@ import chisel3.util.{Valid, log2Ceil}
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import chisel3.util.MuxLookup
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import shapeless.{HNil, ::}
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class ProgramCounter[T <: Data](tpe: T) extends Module {
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class PcControlInterface extends Bundle {
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object SrcSelect extends ChiselEnum {
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val pStaticNpc, pBranchResult = Value
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}
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val control = IO(new Bundle {
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val srcSelect = Input(SrcSelect())
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})
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val in = IO(new Bundle {
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val pcSrcs = Input(Vec(SrcSelect.all.length, tpe))
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})
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val out = Output(tpe)
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out := in.pcSrcs(control.srcSelect.asUInt)
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type ctrlTypes = SrcSelect.Type :: HNil
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def ctrlBindPorts: ctrlTypes = {
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control.srcSelect :: HNil
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srcSelect :: HNil
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}
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}
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class ProgramCounter[T <: Data](tpe: T) extends Module {
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val control = IO(new PcControlInterface)
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val in = IO(new Bundle {
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val pcSrcs = Input(Vec(control.SrcSelect.all.length, tpe))
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})
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val out = IO(Output(tpe))
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out := in.pcSrcs(control.srcSelect.asUInt)
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}
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object ProgramCounter {
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def apply[T <: Data](tpe: T): ProgramCounter[T] = {
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val pc = new ProgramCounter(tpe)
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val pc = Module(new ProgramCounter(tpe))
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pc
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}
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}
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@ -13,6 +13,11 @@ class RegControl extends Bundle {
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val writeEnable = Input(Bool())
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val writeSelect = Input(WriteSelect())
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type ctrlTypes = Bool :: WriteSelect.Type :: HNil
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def ctrlBindPorts: ctrlTypes = {
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writeEnable :: writeSelect :: HNil
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}
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}
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class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
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@ -29,11 +34,6 @@ class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts:
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class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
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val control = new RegControl
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val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
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type ctrlTypes = Bool :: control.WriteSelect.Type :: HNil
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def ctrlBindPorts: ctrlTypes = {
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control.writeEnable :: control.writeSelect :: HNil
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}
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}
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class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
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@ -5,7 +5,7 @@ import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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import flowpc.components._
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import flow.components._
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFileCore" - {
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"register 0 is always 0" in {
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