ysyx-workbench/npc/include/vl_wrapper.hpp

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#ifndef _NPC_TRACER_H_
#define _NPC_TRACER_H_
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#include "components.hpp"
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#include "types.h"
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#include <filesystem>
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#include <gdbstub.h>
#include <sys/types.h>
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#include <verilated_vcd_c.h>
template <class T> class Tracer {
std::shared_ptr<T> top;
std::unique_ptr<VerilatedVcdC> m_trace;
uint64_t cycle = 0;
public:
Tracer(T *top, std::filesystem::path wavefile) {
top = top;
Verilated::traceEverOn(true);
m_trace = std::make_unique<VerilatedVcdC>();
top->trace(m_trace.get(), 5);
m_trace->open(wavefile.c_str());
}
~Tracer() { m_trace->close(); }
/**
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* Dump signals to waveform file. Must be called once after every top->eval()
* call.
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*/
void update() { m_trace->dump(cycle++); }
};
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template <typename T, typename R> class VlModuleInterfaceCommon : public T {
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uint64_t sim_time = 0;
uint64_t posedge_cnt = 0;
std::unique_ptr<Tracer<T>> tracer;
public:
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const R *registers;
VlModuleInterfaceCommon<T, R>() {
tracer = nullptr;
registers = nullptr;
}
void setup(std::filesystem::path wavefile, const R *r) {
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if (!wavefile.empty())
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tracer = std::make_unique<Tracer<T>>(this, wavefile);
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registers = r;
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}
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void eval() {
if (this->is_posedge()) {
posedge_cnt++;
}
T::clock = !T::clock;
sim_time++;
T::eval();
if (tracer)
tracer->update();
}
void eval(int n) {
for (int i = 0; i < n; i++) {
this->eval();
}
}
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gdb_action_t eval(const std::vector<Breakpoint> &breakpoints) {
gdb_action_t res;
do {
this->eval();
size_t pc = registers->get_pc();
for (const auto &bp : breakpoints) {
if (pc == bp.addr) {
res.data = bp.addr;
switch (bp.type) {
default:
res.reason = gdb_action_t::ACT_BREAKPOINT;
}
return res;
}
}
} while (true);
}
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void reset_eval(int n) {
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extern bool g_skip_memcheck;
g_skip_memcheck = true;
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this->reset = 1;
this->eval(n);
this->reset = 0;
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g_skip_memcheck = false;
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}
bool is_posedge() {
// Will be posedge when eval is called
return T::clock == 0;
}
};
#endif