ysyx-workbench/npc/vsrc/example.v

module top(
  input a,
  input b,
  output f
);
  assign f = a ^ b;
endmodule
> sim RTL ysyx_22040000 李心杨 Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec 3 06:32:13 UTC 2023 x86_64 GNU/Linux 18:31:48 up 21:29, 2 users, load average: 1.18, 0.83, 0.63 2023-12-23 10:31:48 +00:00			`module top(`
			`input a,`
			`input b,`
			`output f`
			`);`
			`assign f = a ^ b;`
> sim RTL ysyx_22040000 李心杨 Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec 3 06:32:13 UTC 2023 x86_64 GNU/Linux 17:27:29 up 20:25, 2 users, load average: 0.48, 0.77, 0.76 2023-12-23 09:27:29 +00:00			`endmodule`